# Zynq \u56fe\u50cf\u5904\u7406\u5b9e\u6218\uff1a\u57fa\u4e8e MIPI CSI-2 RX \u7684\u56fe\u50cf\u91c7\u96c6\u4e0e\u5904\u7406\u7cfb\u7edf<\/p>\n
## \u524d\u8a00<\/p>\n
\u5728\u5d4c\u5165\u5f0f\u89c6\u89c9\u5e94\u7528\u4e2d\uff0cXilinx Zynq-7000 SoC \u51ed\u501f\u5176 FPGA+ARM \u7684\u5f02\u6784\u67b6\u6784\uff0c\u6210\u4e3a\u56fe\u50cf\u5904\u7406\u9886\u57df\u7684\u70ed\u95e8\u9009\u62e9\u3002\u672c\u6587\u5c06\u8be6\u7ec6\u4ecb\u7ecd\u5982\u4f55\u4f7f\u7528 Xilinx \u5b98\u65b9 IP \u6838\u642d\u5efa\u4e00\u4e2a\u5b8c\u6574\u7684 MIPI \u56fe\u50cf\u91c7\u96c6\u4e0e\u5904\u7406\u7cfb\u7edf\u3002<\/p>\n
—<\/p>\n
## \u7cfb\u7edf\u67b6\u6784<\/p>\n
“`
\n\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510
\n\u2502 \u56fe\u50cf\u4f20\u611f\u5668 \u2502\u2500\u2500\u2500\u25b6\u2502 MIPI CSI-2 RX \u2502\u2500\u2500\u2500\u25b6\u2502 Demosaic \u2502\u2500\u2500\u2500\u25b6\u2502 Gamma LUT \u2502
\n\u2502 (OV5640) \u2502 \u2502 Subsystem \u2502 \u2502 \u53bb\u9a6c\u8d5b\u514b \u2502 \u2502 \u8272\u5f69\u6821\u6b63 \u2502
\n\u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518
\n \u2502
\n \u25bc
\n\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510 \u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510
\n\u2502 HDMI\/VGA \u2502\u25c0\u2500\u2500\u2500\u2502 Video Timing \u2502\u25c0\u2500\u2500\u2500\u2502 AXI4-Stream\u2502\u25c0\u2500\u2500\u2500\u2502 AXI4 \u603b\u7ebf \u2502
\n\u2502 \u663e\u793a\u5668 \u2502 \u2502 Controller \u2502 \u2502 to Video \u2502 \u2502 (PS \u7aef) \u2502
\n\u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518 \u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518
\n“`<\/p>\n
—<\/p>\n
## \u4e00\u3001MIPI CSI-2 RX Subsystem IP<\/p>\n
### 1.1 IP \u529f\u80fd\u6982\u8ff0<\/p>\n
MIPI CSI-2 RX Subsystem \u662f Xilinx \u63d0\u4f9b\u7684 MIPI \u63a5\u53e3\u63a5\u6536\u7aef\u5b8c\u6574\u89e3\u51b3\u65b9\u6848\uff0c\u652f\u6301\uff1a
\n– **1\/2\/4 Lane \u914d\u7f6e**\uff0c\u6700\u9ad8\u901f\u7387 1.5Gbps\/lane
\n– **YUV420\/YUV422\/RGB \u683c\u5f0f**\u652f\u6301
\n– **\u81ea\u52a8 D-PHY \u65f6\u949f\u68c0\u6d4b**
\n– **AXI4-Stream \u63a5\u53e3\u8f93\u51fa**\uff0c\u4fbf\u4e8e\u540e\u7eed\u5904\u7406<\/p>\n
### 1.2 IP \u914d\u7f6e\u8981\u70b9<\/p>\n
“`
\nClock Mode: Shared Clock
\nNumber of Lanes: 2 Lanes
\nPixel Format: YUV422 8-bit \/ RGB888
\nLine Rate: 1.0 Gbps
\nVideo Format: 1920×1080 @ 30fps
\n“`<\/p>\n
### 1.3 \u5173\u952e\u4fe1\u53f7\u8bf4\u660e<\/p>\n
| \u4fe1\u53f7\u540d | \u65b9\u5411 | \u8bf4\u660e |
\n|——–|——|——|
\n| `mipi_phy_clk` | \u8f93\u5165 | MIPI \u65f6\u949f lane \u5dee\u5206\u8f93\u5165 |
\n| `mipi_phy_data` | \u8f93\u5165 | MIPI \u6570\u636e lane \u5dee\u5206\u8f93\u5165 |
\n| `s_axi_*` | \u8f93\u5165 | AXI-Lite \u914d\u7f6e\u63a5\u53e3 |
\n| `m_axis_video` | \u8f93\u51fa | AXI4-Stream \u89c6\u9891\u6570\u636e\u8f93\u51fa |
\n| `irq` | \u8f93\u51fa | \u4e2d\u65ad\u4fe1\u53f7\uff08\u5e27\u5b8c\u6210\u3001\u9519\u8bef\u7b49\uff09 |<\/p>\n
### 1.4 Vivado \u914d\u7f6e\u622a\u56fe\u4f4d\u7f6e<\/p>\n
“`
\nBlock Design \u2192 MIPI CSI-2 Rx Subsystem \u2192 Re-customize IP
\n\u2192 Stream Interface \u2192 TUSER width: 8 (\u7528\u4e8e\u4f20\u8f93\u6570\u636e\u7c7b\u578b\u6807\u8bc6)
\n“`<\/p>\n
—<\/p>\n
## \u4e8c\u3001Demosaic IP\uff08\u53bb\u9a6c\u8d5b\u514b\u6a21\u5757\uff09<\/p>\n
### 2.1 \u529f\u80fd\u8bf4\u660e<\/p>\n
\u5f53\u4f7f\u7528 Bayer \u683c\u5f0f\u4f20\u611f\u5668\uff08\u5982 OV5640\uff09\u65f6\uff0c\u8f93\u51fa\u4e3a\u5355\u901a\u9053 Bayer \u6570\u636e\uff0c\u9700\u8981\u901a\u8fc7 Demosaic \u7b97\u6cd5\u8f6c\u6362\u4e3a RGB \u4e09\u901a\u9053\u6570\u636e\u3002<\/p>\n
Xilinx \u5b98\u65b9 Demosaic IP \u652f\u6301\uff1a
\n– **Bayer \u8f6c RGB** \u63d2\u503c\u7b97\u6cd5
\n– **\u53cc\u7ebf\u6027\u63d2\u503c**\u548c**\u81ea\u9002\u5e94\u63d2\u503c**\u6a21\u5f0f
\n– **AXI4-Stream \u63a5\u53e3**\uff0c\u6613\u4e8e\u96c6\u6210<\/p>\n
### 2.2 IP \u914d\u7f6e<\/p>\n
“`
\nInput Format: BAYER8 (8-bit Bayer)
\nOutput Format: RGB888
\nInterpolation: Bilinear (\u8d44\u6e90\u5360\u7528\u5c11) \/ Adaptive (\u6548\u679c\u66f4\u597d)
\nMax Resolution: 1920×1080
\n“`<\/p>\n
### 2.3 \u7b97\u6cd5\u539f\u7406<\/p>\n
“`
\nBayer \u6392\u5217\u793a\u4f8b (RGGB):
\nR G R G R G
\nG B G B G B
\nR G R G R G
\nG B G B G B<\/p>\n
\u53cc\u7ebf\u6027\u63d2\u503c\u8ba1\u7b97 G \u5206\u91cf:
\nG(x,y) = (G(x-1,y) + G(x+1,y) + G(x,y-1) + G(x,y+1)) \/ 4
\n“`<\/p>\n
### 2.4 \u8d44\u6e90\u5360\u7528 (Artix-7 XC7A35T)<\/p>\n
| \u8d44\u6e90 | \u5360\u7528 |
\n|——|——|
\n| LUT | ~1,200 |
\n| FF | ~800 |
\n| BRAM | 2 |<\/p>\n
—<\/p>\n
## \u4e09\u3001Gamma LUT IP\uff08\u8272\u5f69\u6821\u6b63\u6a21\u5757\uff09<\/p>\n
### 3.1 Gamma \u6821\u6b63\u539f\u7406<\/p>\n
\u4eba\u773c\u5bf9\u4eae\u5ea6\u7684\u611f\u77e5\u662f\u975e\u7ebf\u6027\u7684\uff0cGamma \u6821\u6b63\u7528\u4e8e\u8865\u507f\u663e\u793a\u8bbe\u5907\u7684\u975e\u7ebf\u6027\u54cd\u5e94\uff1a<\/p>\n
“`
\n\u8f93\u51fa = \u8f93\u5165 ^ (1\/\u03b3)<\/p>\n
\u5178\u578b \u03b3 \u503c\uff1a2.2 (sRGB \u6807\u51c6)
\n“`<\/p>\n
### 3.2 Xilinx Gamma LUT IP \u914d\u7f6e<\/p>\n
“`
\nInput Depth: 10-bit
\nOutput Depth: 10-bit
\nLUT Size: 256 entries (\u53ef\u914d\u7f6e)
\nGamma Value: 2.2 (\u53ef\u52a8\u6001\u914d\u7f6e)
\nColor Space: RGB
\n“`<\/p>\n
### 3.3 LUT \u8868\u751f\u6210 (Python \u793a\u4f8b)<\/p>\n
“`python
\nimport numpy as np<\/p>\n
gamma = 2.2
\nlut_size = 256
\ninput_depth = 10 # 0-1023<\/p>\n
lut = []
\nfor i in range(lut_size):
\n normalized = i \/ (lut_size – 1)
\n corrected = normalized ** (1\/gamma)
\n lut_value = int(corrected * ((2**input_depth) – 1))
\n lut.append(lut_value)<\/p>\n
# \u5bfc\u51fa\u4e3a COE \u6587\u4ef6
\nwith open(‘gamma_lut.coe’, ‘w’) as f:
\n f.write(‘memory_initialization_radix=10;\\n’)
\n f.write(‘memory_initialization_vector=\\n’)
\n f.write(‘,’.join(map(str, lut)) + ‘;’)
\n“`<\/p>\n
### 3.4 \u52a8\u6001\u914d\u7f6e Gamma \u503c<\/p>\n
\u901a\u8fc7 AXI-Lite \u63a5\u53e3\u53ef\u5b9e\u65f6\u4fee\u6539 Gamma \u66f2\u7ebf\uff0c\u5b9e\u73b0\u4e0d\u540c\u573a\u666f\u7684\u8272\u5f69\u9002\u914d\uff1a<\/p>\n
“`c
\n\/\/ PS \u7aef\u914d\u7f6e\u4ee3\u7801\u793a\u4f8b
\nvoid gamma_lut_set_gamma(u32 base_addr, float gamma)
\n{
\n u32 lut[256];
\n for(int i = 0; i < 256; i++) {\n float normalized = (float)i \/ 255.0f;\n float corrected = powf(normalized, 1.0f\/gamma);\n lut[i] = (u32)(corrected * 1023.0f);\n }\n \n \/\/ \u901a\u8fc7 AXI-Lite \u5199\u5165 LUT\n for(int i = 0; i < 256; i++) {\n Xil_Out32(base_addr + i*4, lut[i]);\n }\n}\n```\n\n---\n\n## \u56db\u3001\u5b8c\u6574\u7cfb\u7edf\u96c6\u6210\n\n### 4.1 Block Design \u8fde\u63a5\u56fe\n\n```\n[MIPI CSI-2 RX] \u2500\u2500\u25b6 [Demosaic] \u2500\u2500\u25b6 [Gamma LUT] \u2500\u2500\u25b6 [AXI4-Stream to Video]\n \u2502 \u2502\n \u2502 (AXI-Lite) \u2502 (AXI4-Stream)\n \u25bc \u25bc\n [AXI Interconnect] [Video Timing Ctrl]\n \u2502 \u2502\n \u25bc \u25bc\n [Zynq PS] [HDMI\/VGA]\n```\n\n### 4.2 \u65f6\u949f\u7ea6\u675f\n\n```xdc\n# MIPI \u53c2\u8003\u65f6\u949f (\u901a\u5e38 24MHz \u6216 27MHz)\ncreate_clock -period 37.037 [get_ports mipi_ref_clk]\n\n# \u50cf\u7d20\u65f6\u949f (1080p30 = 74.25MHz)\ncreate_clock -period 13.468 [get_clocks clk_pixel]\n\n# \u7ea6\u675f MIPI D-PHY \u65f6\u949f\nset_property CLOCK_DEDICATED_ROUTE FALSE [get_nets mipi_phy_clk]\n```\n\n### 4.3 \u4e2d\u65ad\u5904\u7406\n\n```c\n\/\/ \u4e2d\u65ad\u670d\u52a1\u51fd\u6570\u793a\u4f8b\nvoid MIPI_Intr_Handler(void *CallbackRef)\n{\n u32 status = Xil_In32(MIPI_BASE + 0x20); \/\/ \u4e2d\u65ad\u72b6\u6001\u5bc4\u5b58\u5668\n \n if(status & 0x01) {\n \/\/ \u5e27\u63a5\u6536\u5b8c\u6210\n frame_ready = 1;\n }\n if(status & 0x02) {\n \/\/ \u5305\u9519\u8bef\n error_count++;\n }\n \n \/\/ \u6e05\u9664\u4e2d\u65ad\n Xil_Out32(MIPI_BASE + 0x20, status);\n}\n```\n\n---\n\n## \u4e94\u3001PS \u7aef\u8f6f\u4ef6\u914d\u7f6e\n\n### 5.1 \u8bbe\u5907\u6811\u914d\u7f6e\n\n```dts\n&axi_mipi_csi2_rx_0 {\n status = \"okay\";\n clocks = <&clkc 15>, <&clkc 16>;
\n clock-names = “lite_aclk”, “pixel_clk”;
\n interrupts = <0 29 4>;
\n};<\/p>\n
&axi_demosaic_0 {
\n status = “okay”;
\n};<\/p>\n
&axi_gamma_lut_0 {
\n status = “okay”;
\n};
\n“`<\/p>\n
### 5.2 V4L2 \u9a71\u52a8\u914d\u7f6e<\/p>\n
“`c
\n\/\/ \u4f20\u611f\u5668\u914d\u7f6e (\u901a\u8fc7 I2C)
\nstruct ov5640_config {
\n u16 width = 1920;
\n u16 height = 1080;
\n u8 format = V4L2_PIX_FMT_YUV422;
\n u8 fps = 30;
\n};<\/p>\n
\/\/ MIPI Lane \u914d\u7f6e
\nmipi_config.lanes = 2;
\nmipi_config.bitrate = 1000000; \/\/ 1Gbps
\n“`<\/p>\n
—<\/p>\n
## \u516d\u3001\u8c03\u8bd5\u6280\u5de7<\/p>\n
### 6.1 ILA \u6293\u53d6\u5173\u952e\u4fe1\u53f7<\/p>\n
“`
\n\u89e6\u53d1\u6761\u4ef6\uff1am_axis_video_tvalid == 1 && m_axis_video_tready == 1
\n\u6293\u53d6\u4fe1\u53f7\uff1a
\n – m_axis_video_tdata[23:0] (RGB \u6570\u636e)
\n – m_axis_video_tvalid
\n – m_axis_video_tready
\n – m_axis_video_tuser[7:0] (\u6570\u636e\u7c7b\u578b)
\n“`<\/p>\n
### 6.2 \u5e38\u89c1\u95ee\u9898\u6392\u67e5<\/p>\n
| \u95ee\u9898 | \u53ef\u80fd\u539f\u56e0 | \u89e3\u51b3\u65b9\u6848 |
\n|——|———-|———-|
\n| \u65e0\u56fe\u50cf\u8f93\u51fa | MIPI \u65f6\u949f\u672a\u9501\u5b9a | \u68c0\u67e5 D-PHY \u65f6\u949f\u7ea6\u675f |
\n| \u56fe\u50cf\u82b1\u5c4f | \u50cf\u7d20\u683c\u5f0f\u4e0d\u5339\u914d | \u786e\u8ba4 Sensor \u8f93\u51fa\u4e0e IP \u914d\u7f6e\u4e00\u81f4 |
\n| \u989c\u8272\u5f02\u5e38 | Gamma LUT \u672a\u521d\u59cb\u5316 | \u68c0\u67e5 AXI \u914d\u7f6e\u662f\u5426\u5b8c\u6210 |
\n| \u5e27\u7387\u4e0d\u7a33\u5b9a | \u65f6\u949f\u4e0d\u540c\u6b65 | \u4f7f\u7528\u540c\u4e00\u65f6\u949f\u6e90 |<\/p>\n
—<\/p>\n
## \u4e03\u3001\u6027\u80fd\u4f18\u5316\u5efa\u8bae<\/p>\n
1. **\u4f7f\u7528 4-Lane MIPI** \u63d0\u5347\u5e26\u5bbd\uff08\u5982\u9700 4K \u5206\u8fa8\u7387\uff09
\n2. **\u542f\u7528 AXI Cache** \u63d0\u9ad8 PS \u7aef\u8bbf\u95ee\u901f\u5ea6
\n3. **\u4f7f\u7528 DDR \u7f13\u5b58** \u5b9e\u73b0\u5e27\u7f13\u51b2\uff08VDMA \u6a21\u5757\uff09
\n4. **\u786c\u4ef6\u52a0\u901f** \u6dfb\u52a0 3A \u7b97\u6cd5\uff08AWB\u3001AE\u3001AF\uff09<\/p>\n
—<\/p>\n
## \u7ed3\u8bed<\/p>\n
\u672c\u6587\u4ecb\u7ecd\u4e86\u57fa\u4e8e Xilinx \u5b98\u65b9 IP \u642d\u5efa Zynq \u56fe\u50cf\u5904\u7406\u7cfb\u7edf\u7684\u5b8c\u6574\u6d41\u7a0b\u3002\u901a\u8fc7 MIPI CSI-2 RX\u3001Demosaic\u3001Gamma LUT \u4e09\u4e2a\u6838\u5fc3\u6a21\u5757\u7684\u914d\u5408\uff0c\u53ef\u5b9e\u73b0\u4ece\u56fe\u50cf\u91c7\u96c6\u5230\u663e\u793a\u7684\u5b8c\u6574\u94fe\u8def\u3002\u8be5\u65b9\u6848\u5df2\u5728\u591a\u4e2a\u9879\u76ee\u4e2d\u9a8c\u8bc1\uff0c\u5177\u6709\u826f\u597d\u7684\u7a33\u5b9a\u6027\u548c\u53ef\u6269\u5c55\u6027\u3002<\/p>\n
—<\/p>\n
**\u53c2\u8003\u8d44\u6e90\uff1a**
\n– Xilinx MIPI CSI-2 RX Subsystem Product Guide (PG232)
\n– Xilinx Demosaic IP Product Guide (PG102)
\n– Xilinx Gamma LUT IP Product Guide (PG107)
\n– Zynq-7000 SoC Technical Reference Manual<\/p>\n","protected":false},"excerpt":{"rendered":"
# Zynq \u56fe\u50cf\u5904\u7406\u5b9e\u6218\uff1a\u57fa\u4e8e MIPI CSI-2 RX \u7684\u56fe\u50cf\u91c7\u96c6\u4e0e\u5904\u7406\u7cfb\u7edf ## \u524d\u8a00 \u5728\u5d4c\u5165\u5f0f\u89c6\u89c9\u5e94 […]<\/p>\n","protected":false},"author":0,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_gspb_post_css":"","footnotes":""},"categories":[32],"tags":[],"class_list":["post-747","post","type-post","status-publish","format-standard","hentry","category-32"],"blocksy_meta":[],"_links":{"self":[{"href":"https:\/\/monykate.com\/index.php\/wp-json\/wp\/v2\/posts\/747","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/monykate.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/monykate.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"replies":[{"embeddable":true,"href":"https:\/\/monykate.com\/index.php\/wp-json\/wp\/v2\/comments?post=747"}],"version-history":[{"count":0,"href":"https:\/\/monykate.com\/index.php\/wp-json\/wp\/v2\/posts\/747\/revisions"}],"wp:attachment":[{"href":"https:\/\/monykate.com\/index.php\/wp-json\/wp\/v2\/media?parent=747"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/monykate.com\/index.php\/wp-json\/wp\/v2\/categories?post=747"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/monykate.com\/index.php\/wp-json\/wp\/v2\/tags?post=747"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}